dl-breadcrumbs__homedl-breadcrumb-item__separatorConfiguration and programmingdl-breadcrumb-item__separator...dl-breadcrumb-item__separatorEngineering interfaces and toolsdl-breadcrumb-item__separatorVirtual commissioning technologydl-breadcrumb-item__separatorSimulation
dl-pagination__prev-inactivedl-pagination__prev-activedl-pagination__next-inactivedl-pagination__next-active
Simulationdl-permalink__symbolPermalink

The simulation runs a program in virtual devices which are selected in Virtual Devices section. The configuration of a system model should be correct to proceed with the simulation. The variable exchange between different devices occurs when the simulation is running.

Without system model, the simulation can be run independently for selected devices. The user can do this when there is no variable data exchange desired.

The simulation supports Free running simulation and Time slice simulation modes. The user need to choose the mode and then launch virtual devices in respective mode. After launching virtual devices, switching to the other mode is not allowed.

Checking signal consistency

Before starting simulation, the signal consistency check is performed on the following criteria.

  • In a System Model, the broken signal should not exist. While configuring System Model, if you delete any mapped model block instance then it will create a broken signal. The user need to clear broken connections using Clear Broken Connection.

  • Any input pin cannot be mapped to multiple output pins.

  • Any mapped signal must have variable associated with it.

  • Variable associated with mapped signal must have a matching data type.

If a configured system model fails to achieve any of these criteria, an error message is shown to the user and the simulation cannot be allowed to continue.

Free running simulation

In Free running simulation, the virtual devices are not synchronized through virtual time. Each device which has participated is running freely. The user can only Start and Stop the simulation. The time elapsed is displayed to indicate the time for which simulation is running.

Fig. 441: Free running simulation
Free running simulation

Before starting simulation, the user need to define:

  • Cycle time: Defines interval for variable data exchange in free running mode.

  • Reset PLC: If selected, earlier state of virtual device will be reset.

Time slice simulation

In Time slice simulation mode, the virtual devices are always synchronized through virtual devices. In this mode, the Steps and Pause buttons are enabled. The user has the two entry points Start or Steps for simulation.

The Virtual time displays the time for which the virtual devices are running. This time is different than that of real time.

Fig. 442: Time slice simulation
Time slice simulation

Before starting simulation, the user need to define:

  • Time Slice (ms): Indicates time for which the virtual devices are running before synchronizing with each other. Also, indicates the time interval for variable data exchange in time slice mode. For example, if the selected time-slice for simulation is 20 ms and scan time of PLC is 10 ms, it means in each time-slice, the PLC executes its program twice.

  • Simulation Speed: Indicates or decides how fast the simulation is executed. The user can change the value even when the simulation is in progress. The simulation speed is independent of time-slice.

  • Reset PLC on start: If selected, earlier state of virtual device is reset.

If variable exchange is not occurring as per expectations, make sure that all the variables defined in system model are available in symbol file. To update symbol file, make sure that the symbol file generation option is selected from CODESYS application (“Project  Options”).